Random access memories (RAM) typically include one or more arrays, with each array having a number of memory cells arranged in rows and columns. In a typical RAM layout, bit lines are disposed along the columns and word lines along the rows. Each memory cell of a row is coupled to a bit line (or bit line pair) by one or more pass transistors. The pass transistors of each row are controlled by a word line. Each word line has an associated word line driver circuit, which drives the word line between a first voltage and a second voltage, to turn the pass transistors on and off, respectively.
Because accessing the cells of a RAM (for either a read or a write operation) requires coupling the bit lines to the memory cells, the speed at which the word line driver can drive a word line between the two voltages can play an important part in the overall speed of the RAM. The goal of providing fast word line drivers, however, is complicated by competing memory design considerations.
RAM memory capacities are continually increasing. Presently, SRAMs of 1 megabit size and DRAMs of 16 megabits are becoming commonplace. Larger memory sizes can lead to longer word lines, creating a more capacitive load for the word line driver. To increase the speed at which the word line driver circuits charge their word lines, it is known to provide a boosted voltage (commonly referred to as Vpp) that is greater than the positive supply voltage. The word line driver circuits then drive their respective word lines between Vpp and a low voltage (Vss).
At the same time RAM capacities are on the rise, RAM device sizes are falling. To reduce the overall physical size of the RAM, the density of devices is pushed to current process limitations (both in the array and the periphery). Accordingly, while higher voltages are provided to increase word line driving speed, this must be accomplished with word line driver circuits having fewer and/or smaller devices.
U.S. Pat. No. 5,363,338 issued to Jong H. Oh on Nov. 8, 1994 discloses a word line driving circuit for a DRAM having four CMOS inverters, each driving a word line. A level shifter commonly drives inputs of the CMOS inverter between a Vpp and a Qss voltage, where Qss is voltage less than zero. By driving the CMOS inverter between Vpp and Qss, the word line can be driven faster than previous word line driver circuits. In the Oh patent, four word lines are commonly decoded, but only one is driven at a given time. This is accomplished by selectively applying Vpp to the pull-up transistor of one of the inverters while the pull-up transistors of the other inverters receive Vss (0 volts). A drawback to the Oh patent is the large number of devices required. Further, the timing circuits required to selectively apply Vpp or Vss to the word line drivers introduces additional complexity to the overall RAM design.
U.S. Pat. No. 5,412,331 issued to Jun et al. on May 2, 1995 discloses a word line driving circuit having an output circuit that includes a CMOS inverter with an additional PMOS transistor gate-coupled to the word line, a transfer circuit for driving the input of the output circuit between a Vpp voltage and Vss (0 volts), a precharge circuit, and a decoder circuit. In one embodiment, the word line is reset to Vss by the precharge circuit, and driven to Vpp by the operation of a word line boosting signal. In another embodiment, the word line is reset to Vss by a precharge transistor coupled to the word line, and driven to Vpp by the operation of a latched level converting circuit. The word line driver circuits of Jun et al. eliminate the need for a clocked Vpp signal, as the word line is driven to Vpp by applying a non-boosted .O slashed.Xi signal to a transfer circuit. Like the word line driver circuit of the Oh patent, the Jun et al. patent requires a large number of devices. In addition, multiple Vpp devices are required per row, as Vpp pull-up devices are used in the decoding circuit 100A, transfer circuit 100C, and output circuit 100D. This adds to the size and complexity of the circuit layout. As is well understood in the art, each of these devices would have to be placed in one or more n-type wells, and be isolated from other p-channel device operating at normal logic levels (Vcc), typically by an n-channel device.
A series of self-boosting word line driver circuits are disclosed in U.S. Pat. No. 5,282,171 issued to Tokami et al. on Jan. 25, 1994. The row driving circuits of Tokami et al. require a clocked Vpp voltage and an input latch of cross coupled p-channel devices, each having a source coupled to the Vpp voltage.
While many approaches to word line driving circuits exist in the prior art, it would be desirable to arrive at a word line driver circuit that addresses the above limitations of the prior art.